Principal Engineer, Device Modeling

Company: Samsung Semiconductor
Location: San Jose
Posted on: February 19, 2026

Job Description:

Job Description Job Description Please Note: To provide the best candidate experience amidst our high application volumes, each candidate is limited to 10 applications across all open jobs within a 6-month period. Advancing the World's Technology Together Our technology solutions power the tools you use every dayincluding smartphones, electric vehicles, hyperscale data centers, IoT devices, and so much more. Here, you'll have an opportunity to be part of a global leader whose innovative designs are pushing the boundaries of what's possible and powering the future. We believe innovation and growth are driven by an inclusive culture and a diverse workforce. We're dedicated to empowering people to be their true selves. Together, we're building a better tomorrow for our employees, customers, partners, and communities. What You'll Do We are looking for experienced technologists who will independently research and explore future logic technology paths, capabilities, and applications through design/system-technology optimization. The candidate will be a key technical member of the Logic Pathfinding Lab, part of the Samsung Semiconductor Inc (SSI) in San Jose. He or she will join a team of experts in researching and evaluating advanced technology options, and assisting in knowledge / technology transfer to the Samsung Logic Technology Development (TD) in Korea. The successful candidate will be responsible for researching and evaluating new device architectures, materials, and integration schemes through chip design metrics to meet the need of sub-3nm technology nodes. The candidate should have strong background on block level PPA analysis and standard cell library generation. The candidate should have excellent communication skills, and be able to collaborate with and guide multiple organizations, including research consortia, to develop internal benchmarking needed in developing a technology roadmap. Location: Daily onsite presence at our San Jose office/headquarters in alignment with our Flexible Work policy Job ID: 42842 Develop and analyze new CMOS and beyond-CMOS device architectures, including the required materials and integrations schemes. Develop internal benchmarking capability based on available data, modeling, and/or learnings from multiple sources, and create assessments to share with internal R&D team. Develop realistic device-level PPAC (power, performance, area, and cost) analysis for new technology options. What You Bring PhD in Electrical Engineering, Mechanical Engineering, Chemical Engineering, Materials Science and Engineering or related fields, and 15 years of industry experience. Conceptualize, design, and assess new CMOS device architectures and logic structures involving new device materials, and process integration. Hands-on experience and understanding of the benefits and limitations of EDA tools in device and process modeling. Expertise in applying Machine Learning algorithms and approaches to accelerate and improve effectiveness of TCAD modeling. Deep knowledge of device physics for 3D logic structures, including emerging beyond-CMOS devices. Develop speculative integration flows and process assumptions, and assess risks. Deep understanding of requirements and design windows for applications including low-power, high-performance, embedded memory. Expertise in design and optimizations of advanced logic and memory standard cells. You're inclusive, adapting your style to the situation and diverse global norms of our people. An avid learner, you approach challenges with curiosity and resilience, seeking data to help build understanding. You're collaborative, building relationships, humbly offering support and openly welcoming approaches. Innovative and creative, you proactively explore new ideas and adapt quickly to change. PREFERRED SKILLS Demonstrated experience and expertise in developing new CMOS device architectures. Understanding of FEOL, MOL, and BEOL process flows. Experience in designing logic test structures and using process emulators. Experience in device reliability assessment. Experience in guiding research consortia funded by the semiconductor industry and / or academic research in the field of device exploration. LI-SF1 What We Offer The pay range below is for all roles at this level across all US locations and functions. Individual pay rates depend on a number of factors—including the role's function and location, as well as the individual's knowledge, skills, experience, education, and training. We also offer incentive opportunities that reward employees based on individual and company performance. This is in addition to our diverse package of benefits centered around the wellbeing of our employees and their loved ones. In addition to the usual Medical/Dental/Vision/401k, our inclusive rewards plan empowers our people to care for their whole selves. An investment in your future is an investment in ours. Give Back With a charitable giving match and frequent opportunities to get involved, we take an active role in supporting the community. Enjoy Time Away You'll start with 4 weeks of paid time off a year, plus holidays and sick leave, to rest and recharge. Care for Family Whatever family means to you, we want to support you along the way—including a stipend for fertility care or adoption, medical travel support, and virtual vet care for your fur babies. Prioritize Emotional Wellness With on-demand apps and free confidential therapy sessions, you'll have support no matter where you are. Stay Fit Eating well and being active are important parts of a healthy life. Our onsite Café and gym, plus virtual classes, make it easier. Embrace Flexibility Benefits are best when you have the space to use them. That's why we facilitate a flexible environment so you can find the right balance for you. Base Pay Range $219,000—$351,000 USD Equal Opportunity Employment Policy Samsung Semiconductor takes pride in being an equal opportunity workplace dedicated to fostering an environment where all individuals feel valued and empowered to excel, regardless of race, religion, color, age, disability, sex, gender identity, sexual orientation, ancestry, genetic information, marital status, national origin, political affiliation, or veteran status. When selecting team members, we prioritize talent and qualities such as humility, kindness, and dedication. We extend comprehensive accommodations throughout our recruiting processes for candidates with disabilities, long-term conditions, neurodivergent individuals, or those requiring pregnancy-related support. All candidates scheduled for an interview will receive guidance on requesting accommodations. Recruiting Agency Policy We do not accept unsolicited resumes. Only authorized recruitment agencies that have a current and valid agreement with Samsung Semiconductor, Inc. are permitted to submit resumes for any job openings. Applicant AI Use Policy At Samsung Semiconductor, we support innovation and technology. However, to ensure a fair and authentic assessment, we prohibit the use of generative AI tools to misrepresent a candidate's true skills and qualifications. Permitted uses are limited to basic preparation, grammar, and research, but all submitted content and interview responses must reflect the candidate's genuine abilities and experience. Violation of this policy may result in immediate disqualification from the hiring process. Applicant Privacy Policy https://semiconductor.samsung.com/about - us/careers/us/privacy/

Keywords: Samsung Semiconductor, Gilroy , Principal Engineer, Device Modeling, Engineering , San Jose, California